The present invention generally relates to a straight line drawing control apparatus, and more particularly to write and read control of image data and address data with respect to buffers provided in a straight line drawing control apparatus.
Referring to FIG. 1, there is illustrated a conventional information processing system which has a straight line drawing control apparatus. The illustrated information processing system is composed of a host computer 1 and a straight line drawing apparatus 2. The straight line drawing apparatus 2 is made up of a host interface 3 which receives data supplied from the host computer 1, a central processing unit (hereinafter simply referred to as a CPU) 5, a straight line drawing control apparatus 6, and an image memory 7, all of which are connected to an internal bus 4. An output signal read out from the image memory 7 is fed to a printer engine 8 such as a laser beam printer.
The host computer 1 creates data relating to characters, graphics or images, and outputs the created data to the internal bus 4 through the host interface 3. Then the CPU 5 interprets the data on the internal bus 4, and derives, therefrom, coordinate data relating to the coordinates of the start and end points of a straight line to be drawn as well as write data relating to luminance and/or color of the straight line. The coordinate data and write data are sent to the straight line drawing control apparatus 6 through the internal bus 4. Then, the straight line drawing control apparatus 6 draws, in the image memory 7, a straight line defined by coordinate data x.sub.1, x.sub.2 and y relating to the start and end points thereof and the write data (FIG. 2). When drawing the straight line is completed, the straight line drawing control apparatus 6 reads out data relating to the drawn straight line from the image memory 7 in accordance with a corresponding instruction supplied from the CPU 5. In this manner, the straight line is printed on a print media such as paper by the printer engine 8.
FIG. 3 is a circuit diagram of the structure for the straight line drawing control apparatus 6. Referring to FIG. 3, the straight line drawing control apparatus 6 is made up of first, second and third latch circuits 11, 12 and 13, a comparator 14, a counter 15, an oscillator 16 and an AND gate 17. The write data labeled DATA supplied from the CPU 5 is written into the third latch circuit 13. The coordinate data x.sub.1, x.sub.2 and y which relate to the start and end points of the straight line to be drawn and are supplied from the CPU 5, are written, as preset data, into the counter 15, the first latch circuit 11 and the second latch circuit 12, respectively. The Y-coordinate data y and the write data DATA are applied to a Y-address input terminal YADR and a write data input terminal WDATA of the image memory 7 as they are. The counter 15 starts counting from the X-coordinate value x.sub.1 and continues to count a clock pulse supplied from the oscillator 16 until a not-equal detection signal is supplied from the comparator 14. The comparator 14 compares the output data from the latch circuit 11 and the output data of the counter 15, and generates the aforementioned detection signal when the outputs are not identical to each other. While the counter 15 continues to count the clock pulse, a write pulse WE is output from the AND gate 17 to the image memory 7, and the not-equal detection signal is supplied, as a busy flag BUSY, to the image memory 7.
During this time, the CPU 5 operates as shown in FIG. 4. The CPU 5 periodically checks the status of the busy flag BUSY (step S1). When the busy flag BUSY is inactive, the CPU 5 sets the write data DATA in the third latch circuit 13 (step S2), and sets the coordinate data y, x.sub.1 and x.sub.2 in the second latch circuit 12, the counter 15 and the first latch circuit 11 (step S3). Then the CPU 5 determines whether the procedure for drawing the designated straight line is completed (step S4). When the result at step S4 is NO, the procedure returns to step S1 and checks the status of the busy flag BUSY. On the other hand, when the result at step S4 is YES, the procedure ends.
Referring to FIG. 5, there is illustrated a different conventional configuration of the straight line drawing control apparatus 6. The first, second and third latch circuits 11, 12 and 13 are replaced by a first-in first-out memory controller (hereinafter simply referred to as an FIFO controller) 18, and first, second, third and fourth first-in first-out memories (hereinafter simply referred to as FIFO memories) 19, 20, 21 and 22. The coordinate data x.sub.1 (start point), x.sub.2 (end point) and y are applied to the third, second and fourth FIFO memories 21, 20 and 22, respectively. The write data DATA is applied to the first FIFO memory 19. A first write clock WCLK1 derived from the CPU 5 is supplied to a write clock terminal WCLK of the second to fourth first FIFO memories 20 to 22 (the terminal WCLK is shown in common therewith for the sake of simplicity). A second write clock WCLK2 derived from the CPU 5 is applied to a write clock terminal WCLK of the first FIFO memory 19. A read clock RCLK1 derived from the FIFO controller 18 is supplied to the first to fourth FIFO memories 19 through 22 through read clock terminals RCLK thereof and to the counter 15. The read clock terminal RCLK of the second FIFO memory 20 is shown in common with the third and fourth FIFO memories 21 and 22 for the sake of simplicity. An output signal from an output terminal OUT of the second FIFO memory 20 is supplied to one (P) of the two input terminals of the comparator 14, and an output signal from an output terminal OUT of the third FIFO memory 21 is supplied to an input terminal P of the counter 15. Data indicating the X address XADR is output from an output terminal Q of the counter 15, and is then supplied to the other input terminal Q of the comparator 14 and the image memory 7. Data indicating the Y address YADR is output from an output terminal OUT of the fourth FIFO memory 22. Write data WDATA is output from an output terminal of the first FIFO memory 19.
The coordinate data x.sub.1, x.sub.2, and y and the write data DATA are supplied from the CPU 5 and written into the third, second, fourth and first FIFO memories 21, 20, 22 and 19, respectively, when a full flag FULL FLG from a terminal FULL of the first FIFO memory 19 is inactive. The FIFO controller 18 outputs the read clock RCLK to the first through fourth FIFO memories 19 through 22 when neither the not-equal detection signal is output nor an empty flag EMPTY FLG from a terminal EMP of the first FIFO memory 19 is active. Thereby, the coordinate data x.sub.1, x.sub.2 and y relating to the start point and end points of the straight line to be drawn and the write data DATA associated therewith are read out from the FIFO memories 21, 20, 22 and 19, respectively. Thereafter, the apparatus shown in FIG. 5 operates in the same manner as the apparatus shown in FIG. 3.
FIG. 6 is a flowchart of a control sequence executed by the CUP 3. The CPU 5 determines whether the full flag FULL FLG output from the first FIFO memory 19 is active (step S11). When the result at step S11 is NO, the CPU 5 sets the write data DATA into the first FIFO memory 19 (step S12), and sets the coordinate data y, x.sub.1 and x.sub.2 into the fourth, third and second FIFO memories 22, 21 and 20, respectively (step S13). Then the CPU 5 discerns whether drawing the straight line to be drawn is completed (step S14). When the result at step S14 is NO, the procedure returns to step S11. The aforementioned procedure consisting of steps S11 to S14 is repeatedly carried out.
However, the conventional configuration of the straight line drawing control apparatus shown in FIG. 2 has the following disadvantages. When drawing the requested straight line is not completed at step S4, the CPU 5 checks the busy flag BUSY at step S1. In this case, if the the busy flag BUSY is active, the CPU 5 must wait for the completion of drawing the straight line. Thus, during this waiting time, the CPU 5 is not permitted to execute any operation. From this reason, the configuration shown in FIG. 2 needs a long processing time.
The configuration of the straight line drawing control apparatus shown in FIG. 5 has the following disadvantages. The CPU 5 can set write data DATA in the first FIFO memory 19 until the full flag FULL FLG output from the FIFO memory 19 becomes active. However, the configuration shown in FIG. 5 needs FIFO memories each having the same number of stages for the write data DATA and the coordinate data y, x.sub.1 and x.sub.2. For this reason, there is a need for a large memory capacity. The write data DATA and the coordinate data x.sub.1, x.sub.2 and y are simultaneously written into the corresponding FIFO memories without exception. From this point of view, even when write data of a next straight line to be drawn is the same as that in the previous processing, the same write data must be written in the first FIFO memory 19 again. Such a data writing procedure causes a delay of the processing speed.